1. Field
Embodiments discussed herein relate to a latch circuit including a data input terminal and a scan data input terminal, and a semiconductor device and a control method.
2. Description of the Related Art
For a D-latch (Data latch) circuit to be provided with a scanning function for a test or initial setting use, a first latch is sometimes provided with a second latch that is not used for the normal operation. In this case, the second latch is driven by a scan clock, which is different from a system clock in charge of system operation.
FIG. 7 depicts an exemplary circuit configuration of a previous D-latch circuit having a scanning function. This D-latch circuit is configured to include scan clock input terminals 11 and 15, a clock input terminal 12, a data input terminal 13, a scan data input terminal 14, switches 16, 17, and 19, latch sections 18 and 20, buffers 21 and 22, and data output terminals 23 and 24. Among these components, the switches 16 and 17, and the latch section 18 configure a first latch, and the switch 19 and the latch section 20 configure a second latch.
The scan clock input terminals 15 and 11 are respectively provided with a first scan clock signal SCANCLK_A and a second scan clock signal SCANCLK_B. The clock input terminal 12 is provided with a clock signal CLK, and the data input terminal 13 is provided with a data signal DATA_IN. The scan data input terminal 14 is provided with a scan data signal SCAN_IN.
The switch 16 is turned ON when the clock signal CLK is in a high level (H), and is turned OFF when the clock signal CLK is in a low level (L). The switch 17 is turned ON when the scan clock signal SCANCLK_A is in H, and is turned OFF when the scan clock signal SCANCLK_A is in L. The latch section 18 holds the value of an input signal, and forwards the value to both the switch 19 and the buffer 22. As such, when either the clock signal CLK or the scan clock signal SCANCLK_A is in H, an input signal to the switch 16 or 17 is transmitted to an output terminal of the latch section 18, and when either the clock signal CLK or the scan clock signal SCANCLK_A is in L, an output signal of the latch section 18 is kept.
The switch 19 is turned ON when the scan clock signal SCANCLK_B is in H, and is turned OFF when the scan clock signal SCANCLK_B is in L. The latch section 20 holds the value of an input signal, and outputs the value to the buffer 21. As such, when the scan clock signal SCANCLK_B is in H, an input signal to the switch 19 is transmitted to an output terminal of the latch section 20, and when the scan clock signal SCANCLK_B is in L, an output signal of the latch section 20 is kept.
The buffers 21 and 22 respectively forward the input signals to the data output terminals 23 and 24 after delaying the signals by a predetermined length of time.
For using such a D-latch circuit, there are the following two ways, for example.
1. First Use
During the normal operation, a scan clock signal SCANCLK_A is set to L, and the first latch is driven by a clock signal CLK. A scan clock signal SCANCLK_B is then set to H so that the second latch is set to be in the through state, and the output data from the first latch is forwarded to the data output terminal 23 as it is. In this case, the data output terminal 23 provides a master data signal MASTER2, which is used as slow-speed master data in a circuit in the subsequent stage. Similarly, the data output terminal 24 provides a master data signal MASTER1, which is used as fast-speed master data in the circuit in the subsequent stage.
On the other hand, during the scanning operation, a clock signal CLK is set to L, and the first latch is driven by a scan clock signal SCANCLK_A. The second latch is driven by a scan clock signal SCANCLK_B. In this case, the data output terminal 23 provides a scan data signal as a scan out data signal.
2. Second Use
During the normal operation, a scan clock signal SCANCLK_A is set to L, and the first latch is driven by a clock signal CLK. A scan clock signal SCANCLK_B is then set to L, thereby closing the second latch. In this case, the data output terminal 24 forwards only the master data signal MASTER1 to the circuit in the subsequent stage.
On the other hand, during the scan operation, a clock signal CLK is set to L, and the first latch is driven by a scan clock signal SCANCLK_A. The second latch is driven by a scan clock signal SCANCLK_B. In this case, the data output terminal 23 forwards a scan data signal as a scan out data signal.
FIG. 8 depicts an exemplary detailed configuration of the D-latch circuit of FIG. 7. This D-latch circuit is configured to include a clock input terminal 31, a scan clock input terminals 32 and 34, a data input terminal 35, a scan data input terminal 33, and data output terminals 81 and 82.
The D-latch circuit is also provided with P-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) 41, 43, 46, 48, 50, 51, 54, 56, 58, 60, 62, 63, 66, 68, 70, and 72. The D-latch circuit is also provided with N-channel MOSFETs 42, 44, 47, 49, 52, 53, 55, 57, 59, 61, 64, 65, 67, 69, 71, and 73. The D-latch circuit is also provided with a transfer gate 45.
In the below, the P-channel MOSFETs and the N-channel MOSFETs are respectively denoted as PMOSs and NMOSs. The source electrodes of the PMOSs 41, 43, 46, 48, 50, 54, 56, 58, 60, 62, 66, 68, 70, and 72 are each connected to a power supply potential VDD, and the source electrodes of the NMOSs 42, 44, 47, 49, 53, 55, 57, 59, 61, 65, 67, 69, 71, and 73 are each connected to a ground potential.
The clock input terminal 31 is provided with an inverted clock signal ICLK being a result of inverting the clock signal CLK, and the scan clock input terminals 32 and 34 are respectively provided with the scan clock signals SCANCLK_A and SCANCLK_B. The data input terminal 35 and the scan data input terminal 33 are respectively provided with a data signal DATA_IN and a scan data signal SCAN_IN. From a data output terminal 81, the master data signal MASTER1 is provided, and from a data output terminal 82, the master data signal MASTER2 or the scan out data signal is provided.
The PMOS 41 and the NMOS 42 configure an inverter, which inverts the inverted clock signal ICLK for output to an NMOS-side gate electrode 75 of the transfer gate 45. The inverted clock signal ICLK is provided to a PMOS-side gate electrode 74 of the transfer gate 45. The PMOS 43 and the NMOS 44 also configure an inverter, which inverts the data signal DATA_IN for output to the input terminal of the transfer gate 45.
The transfer gate 45 forwards an input data signal from the output terminal as a data signal PCM1 when the PMOS-side gate electrode 74 and the NMOS-side gate electrode 75 are respectively put in L and H.
The PMOS 46 and the NMOS 47 configure an inverter, which inverts the data signal PCM1, and outputs the master data signal MASTER1.
The PMOSs 48, 50, and 51, and the NMOSs 49, 52, and 53 configure a clocked inverter, which inverts a scan data signal SCAN_IN when the scan clock signal SCANCLK_A is in H, thereby outputting a data signal PCM1.
The PMOS 54 and the NMOS 55 configure an inverter, which inverts the data signal PCM1, thereby outputting a data signal PAM1. The PMOS 56 and the NMOS 57 configure an inverter, which inverts the data signal PAM1, thereby outputting a data signal PCM1. The PMOSs 54 and 56, and the NMOSs 55 and 57 correspond to the latch section 18 of FIG. 7.
The PMOS 58 and the NMOS 59 configure an inverter, which inverts the scan clock signal SCANCLK_B for output. The PMOSs 60, 62, and 63, and the NMOSs 61, 64, and 65 configure a clocked inverter, and when the signal being a result of inverting the scan clock signal SCANCLK_B is in L, i.e., when the scan clock signal SCANCLK_B is in H, inverts the data signal PAM1, thereby outputting a data signal PCS1.
The PMOS 66 and the NMOS 67 configure an inverter, which inverts the data signal PCS1 for output. The PMOS 68 and the NMOS 69 configure an inverter, which inverts the data signal provided by the PMOS 66 and the NMOS 67, thereby outputting the data signal PCS1. The PMOSs 66 and 68, and the NMOSs 67 and 69 correspond to the latch section 20 of FIG. 7.
The PMOS 70 and the NMOS 71 configure an inverter, which inverts the data signal provided by the PMOS 66 and the NMOS 67 for output. The PMOS 72 and the NMOS 73 configure an inverter, which inverts a data signal provided by the PMOS 70 and the NMOS 71, thereby outputting a master data signal MASTER2 or scan out data signal.
The transfer gate 45 corresponds to the switch 16 of FIG. 7, and the clocked inverter including the PMOSs 48, 50, 51, and the NMOSs 49, 52, and 53 correspond to the switch 17 of FIG. 7. Similarly, the clocked inverter including the PMOSs 60, 62, and 63, and the NMOSs 61, 64, and 65 correspond to the switch 19 of FIG. 7.
A pulse latch circuit is also known, which includes the first and second latches, and stops the supply of a clock signal to the second latch when no scan test is performed. A flip-flop circuit is also known, in which a slave latch is provided with a transmission gate, and a mode signal makes the transmission gate non-conductive. A D-flip-flop (Data flip-flop) circuit is also known, which cuts off a signal supply from any periphery circuit by closing a transfer gate of a master section during the normal operation.    [Patent Document 1] Japanese Laid-Open Patent Publication No. 2006-339948    [Patent Document 2] Japanese Laid-Open Patent Publication No. 09-270677    [Patent Document 3] Japanese Laid-Open Patent Publication No. 2005-221352